1. Technical Field
The present disclosure relates to the management of the electrical power supply of systems such as integrated circuits. The present disclosure particularly applies to Systems on Chip (SoC).
2. Description of the Related Art
Recently, particularly with the development of mobile systems, the current consumption of circuits has become a key constraint when designing architectures of systems such as microprocessors. Furthermore, the increasing miniaturization of integrated circuits tends to reduce the threshold voltages of transistors and thus to increase leakage currents. Therefore, the current consumption due to leakage currents tends to become comparable to the current consumption resulting from the activity of a microprocessor. Traditionally, priority was given to the computing power. As a result, the supply voltage was set at the maximum possible value. However, many applications executed by a microprocessor do not continuously require a maximum computing power. Thus, an application designed to receive for example user commands or data from a telecommunications network, can often find itself waiting for commands or data. During these waiting periods, the application does not require a maximum computing power.
It has therefore been suggested to use such periods of low activity of a circuit to reduce the supply voltage, and thus reduce the current consumption of the circuit. Methods for adapting the supply voltage such as AVS (Adaptative Voltage Scaling) and DVS (Dynamic Voltage Scaling) have been developed to adapt the supply voltage of a system such as a microprocessor to the activity of the latter. These methods prove efficient in reducing the current consumption, but do not efficiently reduce the leakages occurring in the circuits, particularly when the activity of the microprocessor is low. These methods require the clock frequency of the system to be adapted at the same time as the supply voltage, which implies a transition time to change between two levels of supply voltage that can reach several hundred microseconds. Such a time can be unacceptable in certain applications.
Therefore methods for adapting the body biasing of transistors known as Adaptive Body Biasing (ABB), particularly to reduce leakage currents, have also been proposed. Some of these methods, called RBB (Reverse Body Biasing), involve biasing the bodies of n-channel MOS transistors of a circuit to a negative bias voltage (lower than the ground of the circuit), and the bodies of p-channel MOS transistors to a voltage greater than the supply voltage of the circuit. RBB-type methods enable the current leakages to be reduced, at constant supply voltage, but cause an increase in the threshold voltage of the transistors and thus a decrease in the processing speed. Other methods called FBB (Forward Body Biasing) involve biasing the bodies of the n-channel MOS transistors in a circuit to a bias voltage greater than the ground of the circuit, and the p-channel MOS transistors to a bias voltage lower than the supply voltage of the circuit. FBB-type methods enable the threshold voltage of the transistors to be decreased and thus the processing speed of a circuit to be increased, or the supply voltage of the circuit to be decreased without reducing the processing speed.
Systems on chip generally include several integrated circuits on a same chip. To reduce the current consumption of a system on chip, all the circuits of the system are not necessarily all supplied with power continuously. As a result, the load impedance of the power supply circuit of the system varies according to the size of the area of the system supplied with power at a given instant. It is therefore difficult to integrate a power supply circuit into a system on chip. This is why the power supply circuit of such a system is often remote and at least partly located in another integrated circuit which can be connected to the system, for example through conductive paths formed on a substrate such as a printed circuit board on which the system and its power supply circuit, as well as capacitors are arranged.
FIG. 1 schematically represents a system on chip SS1 and its power supply circuit PGEN. The circuit PGEN includes a terminal for providing the supply voltage Vdd and a ground terminal Gnd. The terminals receiving the voltages Vdd and Gnd can be linked to supply terminals of the system SS1, by conductive paths formed on a substrate such as a printed circuit board PCB. Each of these conductive paths is linked to the ground of the substrate (e.g., printed circuit) through a capacitor Cv, Cg also installed on the substrate (e.g., printed circuit board). The system SS1 includes several circuits. For the sake of clarity, only one of these circuits, of the system processing unit PU type, is represented. Each of these circuits and particularly the unit PU receives the supply voltage Vdd through a switch formed for example by a transistor Ml, and the ground voltage Gnd. The transistor Ml is controlled so as to be on when the processing unit PU must be power supplied. The capacitors Cv, Cg which represent a capacitance in the order of 0.1 to 1 μF, enable the load impedance of the voltage generating circuits of the circuit PGEN to be set to a value substantially independent of the size of the area of the system SS1 to be power supplied at a given instant. The capacitance of the capacitors Cv, Cg depends on the maximum power to be provided by the circuit PGEN.
The method ABB can be implemented in the circuit in FIG. 1 by providing that the circuit PGEN supplies body bias voltages Vbn, Vbp of n- and p-channel MOS transistors of the system SS1. Like for the voltages Vdd and Gnd, the voltages Vbn and Vbp are provided by links connected to the ground through capacitors Cn, Cp having a capacitance in the order of 0.1 to 1 μF. The capacitors Cv, Cg, Cn, Cp form, together with the conductive paths between the circuit PGEN and the system SS1, impedances introducing relatively high time constants. The voltages Vdd, Vbn and Vbp cannot therefore be changed by the circuit PGEN to follow the fast changes in the activity of the system SS1 with a sufficiently short response time, which varies according to the application implemented by the system. For an application involving short, frequent periods of activity, for example of Web surfing type, this response time may be lower than 200 ns. Given the frequency of the periods of activity, a higher response time would amount to operating the system with a lower clock frequency and thus to increasing the operating time of the system. As a result, the current consumption gain would be lower. In addition, a higher response time would also be disadvantageous for the user and the operating system of the system on chip.
The links between the circuits PGEN and SS1 and the capacitors introduce relatively high time constants, preventing fast changes to the supply voltage Vdd provided by the circuit PGEN, for example according to the activity of the system SS1.
FIGS. 2A, 2B are timing diagrams of variations in the activity and in the electrical power consumption of the processing unit PU. The variations in the electrical power in FIG. 2B relate to the activity of the processing unit PU indicated by the timing diagram in FIG. 2A. In FIG. 2A, the activity of the processing unit PU has periods of activity R spaced out by waiting periods or periods of relatively low activity W during which the unit PU is waiting for an external event, for example the arrival of a data stream by a communication interface or a command from a user interface device. In FIG. 2B, the electrical power PM consumed by the unit PU is maximum during the periods of activity R. During the waiting periods W, the electrical power consumption of the unit PU has a value PL which can be between a quarter and a third of the maximum power consumption. The power PL is mainly due to the leakage currents of the circuit, while the power PM is equal to the sum of the power D consumed by the circuit due to its activity and the power PL. The waiting periods W may represent a high proportion of the total time which can reach values between 50% and 90%. During the periods W, the data must be kept in the memories and registers of the unit PU, and the flip-flops of the unit PU must keep the same state. During certain periods of inactivity, the unit PU must be able to reach a high activity in a minimum amount of time, which may be lower than 200 ns. Therefore, the supply voltage Vdd of the processing unit cannot be cut off or reduced. The result is that during a given period, the leakage electrical power may be greater than the electrical power consumed by the unit PU due to its activity.
It is therefore desirable to reduce the current leakages without reducing the computing power of a system, particularly of a system powered by an external circuit. It is also desirable to be able to adapt the electrical power supply of a system according to the activity of the latter with response times lower than the time constants of the power supply connections of the system, so as to reduce the current consumption of the system.